Multi-phase reference clock signals, such as four-phase reference clocks, are used in many processing systems to sample signals. In some high-speed input/output (I/O) data recovery circuit (DRC) applications, reference clock signals are used to regenerate receiver sampling clock signals to track the phase of a received data stream. Non-idealities present in these reference clock signals, such as static phase error, duty cycle error, and/or jitter, resulting from link timing margin degradation may result in degraded I/O bit-error-rate (BER).
Thus, there are general needs for methods and circuits that correct and/or reduce the non-idealities present in multi-phase reference clock signals. There are also needs for data recovery circuits with reduced BER.